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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ad9860/ad9862 * mixed-signal front-end (mxfe ) processor for broadband communications * protected by u.s.patent no. mxfe is a trademark of analog devices, inc. general description the ad9860 and ad9862 (ad9860/ad9862) are versatile integrated mixed-signal front-ends (mxfe) that are optimized for broadband communication markets. the ad9860/ad9862 are cost effective, mixed signal solutions for wireless or wireline standards based or proprietary broadband modem systems where dynamic performance, power dissipation, cost, and size are all critical attributes. the ad9860 has 10-bit adcs and 12-bit dacs; the ad9862 has 12-bit adcs and 14-bit dacs. the ad9860/ad9862 receive path (rx) consists of two channels that each include a high performance, 10-/12-bit, 64 msps analog- to-digital converter (adc), input buffer, progra mmable gain amplifier (rxpga), digital hilbert filter, and decimation filter. the rx can be used to receive real, diversity, or i/q data at baseband or low if. the input buffers provide a constant input impedance for both channels to ease impedance matching with external com- ponents (e.g., saw filter). the rxpga provides a 20 db gain range for both channels. the output data bus can be multi- plexed to accommodate a variety of interface types. the ad9860/ad9862 transmit path (tx) consists of two chan- nels that contain high performance, 12-/14-bit, 128 msps digital-to- analog converters (dac), programmable gain amplifiers (txpga), interpolation filters, a hilbert filter, and digital mixers for complex or real signal frequency modulation. the tx latch and demultiplexer circuitry can process real or i/q data. interpo- lation rates of 2 and 4 are available to ease requirements on an external reconstruction filter. for single channel systems, the digital hilbert filter can be used with an external quadrature modulator to create an image rejection architecture. the two 12-/14-bit, high performance dacs produce an output signal that can be scaled over a 20 db range by the txpga. a programmable delay-locked loop (dll) clock multiplier and integrated timing circuits enable the use of a single external reference clock or an external crystal to generate clocking for all internal blocks and also provides two external clock outputs. additional features include a programmable sigma-delta output, four auxiliary adc inputs and three auxiliary dac outputs. device programmability is facilitated by a serial port interface (spi) combined with a register bank. the ad9860/ad9862 is available in a space saving 128-lead lqfp. functional block diagram tx data [0:13] pga pga dac dac hilbert filter logic low adc adc pga pga 1x 1x iout+a iout? iout+b iout? au x_adc_b2 au x_adc_b1 au x_adc_a2 au x_adc_a1 aux_ dac_c aux_ dac_b aux_ dac_a sigdelt vin+a vin? vin+b vin? - aux dac aux dac aux dac aux adc aux adc rxa data [0:11] rxb data [0:11] spi interface osc1 osc2 clkout1 clkout2 spi registers clock distribution block dll 1 , 2 , 4 rx path timing tx path timing ad9860/ad9862 hilbert filter bypassable digital qu adrature mixer bypassable digital qu adrature mixer bypassable low-pass interpolation filter nco fs/4 fs/8 bypassable low-pass decimation filter features mixed-signal front-end processor with dual converter receive and dual converter transmit signal paths receive signal path includes: two 10-/12-bit, 64 msps sampling a/d converters with internal or external independent references, input buffers, programmable gain amplifiers, low-pass decimation filters, and a digital hilbert filter transmit signal path includes: two 12-/14-bit, 128 msps d/a converters with programmable full-scale output current, channel independent fine gain and offset control, digital hilbert and interpolation filters, and digitally tunable real or complex up-converters delay-locked loop clock multiplier and integrated timing generation circuitry allow for single crystal or clock operation programmable output clocks, serial programmable interface, programmable sigma-delta, three auxiliary dac outputs and two auxiliary adcs with dual mul tiplexed inputs applications broadband wireless systems fixed wireless, wlan, mmds, lmds broadband wireline systems cable modems, vdsl, powerplug digital communications set-top boxes, data modems
rev. 0 ?2? ad9860/ad9862especifications (v a = 3.3 v 5%, v d = 3.3 v 10%, f dac = 128 mhz, f adc = 64 mhz normal timing mode, 2 dll setting, r set = 4 k , 50 dac load, rxpga = +6 db gain, txpga = +20 db gain.) test ad9860/ad9862 tx parameters temp level min typ max unit 12-/14-bit dac characteristics resolution na na 12/14 bits maximum update rate 128 msps full-scale output current full i 2 20 ma gain error (using internal reference) 25 o C o C o C o C C o o 1/ 3 lsb output capacitance 25 o o C C o o 0.1 db step size 25 o 38 % f data dynamic performance (a out = 20 ma fs, f = 1 mhz) differential phase 25 o o C C o o o o o C C o o o o o w input capacitance (each input) full iii 5 pf maximum input bandwidth ( C o 0.3 db gain range 25 o o 0.2 db step size 25 o C o
rev. 0 ad9860/ad9862 ?3? test ad9860/ad9862 rx parameters (continued) temp level min typ max unit dc accuracy differential nonlinearity 25 o 0.3/ 0.4 lsb integral nonlinearity 25 o 1.2/ 5 lsb offset error 25 o 0.1 %fsr gain error 25 o 0.2 %fsr aperture delay 25 o o o o 1 4mv ad9860 dynamic performance (a in = C C C C C C o o o C o o o o o C o o o o o o o o o o o o o o o o
rev. 0 ?4? ad9860/ad9862 test ad9860/ad9862 (20 pf load) temp level min typ max unit minimum reset pulsewidth low (t rl )nana5 clock cycles digital output rise/fall time 25 o o o C C o o o o o o o o m s output range 25 o o o o o o o o o o o o o o
rev. 0 ad9860/ad9862 ?5? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9860/ad9862 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 power supply (v as , v ds ) . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma digital inputs . . . . . . . . . . . . . . . . C C C C C o C o o o C C C
rev. 0 ?6? ad9860/ad9862 pin configuration 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 33 34 35 36 38 31 37 a gnd av d d dvdd dgnd dgnd dvdd tx11/13 (msb) tx10/12 39 40 41 42 43 44 45 46 47 48 49 50 63 64 61 62 59 60 57 58 55 56 53 54 51 52 76 77 78 79 74 75 72 73 70 71 80 65 66 67 68 69 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a gnd av d d av d d au x_spi_csb aux_ spi_clk aux_ spi_do dgnd dvdd rxsync d9/d11b (msb) d8/d10b d7/d9b d6/d8b d5/d7b d4/d6b d3/d5b d2/d4b d1/d3b d0/d2b nc/d1b pin 1 identifier top view (not to scale) tx9/11 tx8/10 tx7/9 tx6/8 tx5/7 tx4/6 tx3/5 tx2/4 tx1/3 tx0/2 nc/tx1 nc/tx0 nc/d0b d9/d11a (msb) d8/d10a d7/d9a d6/d8a d5/d7a d4/d6a d3/d5a d2/d4a d1/d3a d0/d2a nc/d1a nc/d0a dgnd dvdd clkout1 au x_adc_a1 a gnd av d d av d d sigdelt aux_ da c_a aux_ da c_b aux_ da c_c a gnd dll_lock a gnd nc av d d osc1 osc2 a gnd clksel av d d a gnd av d d refio fsadj av d d a gnd ioutea iout+a a gnd a gnd iout+b iouteb ad9860/ad9862 txsync dgnd dvdd sclk sdo sdio sen dgnd dvdd dgnd dvdd mode/txblank resetb clkout2 reft_b refb_b 101 102 128 127 126 125 124 123 122 121 120 119 118 117 104 103 106 105 108 107 110 109 112 111 114 113 116 115 a gnd av d d av d d a gnd vin+b vineb a gnd a gnd vref a gnd a gnd vinea vin+a a gnd av d d av d d a gnd refb_a reft_a a gnd av d d av d d au x_adc_b2 au x_adc_b1 au x_adc_ref au x_adc_a2 nc = no connect
rev. 0 ad9860/ad9862 ?7? pin no. mnemonic function clock pins 10 dll_lock dll lock indicator pin 11, 16 agnd dll analog ground pins 12 nc no connect 13 avdd dll analog supply pin 14 osc1 single ended input clock (or crystal oscillator input) 15 osc2 crystal oscillator input 17 clksel controls clkout1 rate 64 clkout2 clock output generated from input clock (dll mu ltiplier setting and clkout2 divide factor) 65 clkout1 clock output generated from input clock (1 if clksel = 1 or /2 if clksel = 0) various pins 1 aux_adc_a1 auxiliary adc a input 1 3, 4, 13 avdd analog power pins 2, 9 agnd analog ground pins 5 sigdelt digital output from programmable sigma-delta 6 aux_dac_a auxiliary dac a output 7 aux_dac_b auxiliary dac b output 8 aux_dac_c auxiliary dac c output 33, 36, 53, dvdd digital power supply pin 59, 61, 66, 93 34, 35, 52, dgnd digital ground pin 58, 60, 67, 94 54 sclk serial bus clock input 55 sdo serial bus data bit 56 sdio serial bus data bit 57 sen serial bus enable 63 resetb reset (spi registers and logic) 95 aux_spi_do optional auxiliary adc serial bus data out bit 96 aux_spi_clk optional auxiliary adc serial bus data out latch clock 97 aux_spi_csb optional auxiliary adc serial bus chip select bit 128 aux_adc_a2 auxiliary adc a input 2 126 aux_adc_b1 auxiliary adc b input 1 125 aux_adc_b2 auxiliary adc b input 2 127 aux_adc_ref au xiliary adc reference pin no. mnemonic function receive pins 68/70 C C C C C C C
rev. 0 ?8? ad9860/ad9862 definitions of specifications differential nonlinearity error (dnl, no missing codes) an ideal converter exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 10-bit resolution indicate that all 1024 codes respectively, must be present over all operating ranges. integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from C C sinad can be expressed in terms of the number of bits. using the following formula: n = () sinad db C n , the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. power supply rejection power supply rejection specifies the converter
rev. 0 t ypical performance characteristicsead9860/ad9862 ?9? frequency e mhz 0 magnitude e dbm 0 e20 e40 20 40 60 80 100 110 120 e60 e80 e100 140 e90 e70 e50 e30 e10 f data = 32msps 4 interpolation tpc 1. ad9862 tx output 6 mhz single tone; clkin = 32 mhz; dll 4 setting frequency e mhz 0 magnitude e dbm 0 e20 e40 20 40 60 80 100 110 120 e60 e80 e100 140 e120 f data = 32msps 1 interpolation tpc 4. txdac generating an ofdm signal; clkin = 64 mhz, dll 2 setting f out e mhz 52035 e60 e65 e70 e75 e80 e85 e90 10 15 25 30 thd e dbc f data = 64msps 2 interpolation thd 2nd 3rd tpc 7. txdac harmonic distortion vs. f out frequency e mhz 0 magnitude e dbm 0 e20 e40 20 40 60 80 100 110 120 e60 e80 e100 140 e90 e70 e50 e30 e10 f data = 32msps 4 interpolation tpc 2. ad9862 tx output 6 mhz single tone; clkin = 64 mhz; dll 2 setting frequency e mhz 0 magnitude e dbm 0 e20 e40 20 40 60 80 100 110 120 e60 e80 e100 140 e120 f data = 32msps 4 interpolation tpc 5. txdac generating an ofdm signal; clkin = 64 mhz, dll 2 setting frequency e mhz 5 snr e db 20 74 10 15 25 30 73 72 71 70 69 68 0 f data = 64msps 2 interpolation ad9862 ad9860 tpc 8. signal-to-noise ratio (snr) vs. f out frequency e mhz 0 magnitude e dbm 0 e20 e40 20 40 60 80 100 110 120 e60 e80 e100 140 e90 e70 e50 e30 e10 f data = 32msps 4 interpolation tpc 3. ad9862 tx output 6 mhz single tone; clkin = 128 mhz; dll 1 setting frequency e mhz 7.90 magnitude e dbm 0 e20 e40 e60 e80 e100 e120 7.92 7.94 7.96 7.98 8.00 8.02 8.04 8.06 8.08 f data = 32msps 4 interpolation tpc 6. zoomed in plot of four notched carriers of ofdm signal; clkin = 64 mhz, dll 2 setting carrier frequency e mhz 5 imd e dbc 20 e60 e65 e70 e75 e80 e85 e90 10 15 25 30 e50 e55 e95 av d d = 3.0v av d d = 3.3v av d d = 3.6v f data = 64msps 2 interpolation tpc 9. two tone intermodulation vs. f out1 (f out2 = f out1 + 1 mhz)
rev. 0 ?10? ad9860/ad9862 fft output e mhz 5 fft magnitude e dbfs 20 e20 e40 e60 e80 10 15 25 30 0 e100 e120 0 tpc 10. adc dual tone fft with buffer tones at 4.5 mhz and 5.5 mhz f in e mhz 0 200 50 60 58 56 54 50 62 11.0 8.0 8.5 10.0 10.5 9.5 9.0 150 250 100 64 66 68 bu ffered 1v input, 2 gain bu ffered 2v input, 1 gain bu ffered bypass 1v input, 2 gain bu ffered bypass 2v input, 1 gain 52 300 tpc 13. ad9862 rx sinad vs. f in at 64 msps f in e mhz 0 200 50 60 58 56 54 52 50 48 62 46 44 10.0 7.0 7.5 9.0 9.5 8.5 8.0 150 250 100 bu ffered bypass 1v input, 2 gain bu ffered 1v input, 2 gain bu ffered bypass 2v input, 1 gain bu ffered 2v input, 1 gain 300 tpc 16. ad9860 rx sinad vs. f in at 64 msps fft output e mhz 5 fft magnitude e dbfs 20 e20 e40 e60 e80 10 15 25 30 0 e100 e120 0 tpc 11. adc dual tone fft without buffer tones at 4.5 mhz and 5.5 mhz f in e mhz 0 200 50 sinad e dbc 60 58 56 54 52 50 62 150 250 100 64 66 68 70 300 low power mode 1, buffer bypassed, 2v p-p input, 1 rxpga gain bu ffer bypassed, 2v p-p, 1 rxpga gain low power mode 1, buffer enabled, 1v p-p input, 2 rxpga gain buff er enabled, 1v p-p input, 2 rxpga gain tpc 14. ad9862 rx sinad vs. f in at 32 msps f in e mhz 0 200 50 sinad e dbc 52 50 48 46 44 54 150 250 100 56 58 60 62 300 low power mode 1, buffer bypassed, 2v p-p input, 1 rxpga gain bu ffer bypassed, 2v p-p, 1 rxpga gain low power mode 1, buff er enabled, 1v p-p input, 2 rxpga gain bu ffer enabled, 1v p-p input, 2 rxpga gain tpc 17. ad9860 rx sinad vs. f in at 32 msps fft output e mhz 5 fft magnitude e dbfs 20 e20 e40 e60 e80 10 15 25 30 0 e100 e120 0 tpc 12. adc dual tone fft (undersampling) without buffer tones at 69.5 mhz and 70.5 mhz f in e mhz 0 200 50 sinad e dbc 60 58 56 54 52 50 62 150 250 100 64 66 68 70 300 low power mode 2, buffer bypassed, 2v p-p input, 1 rxpga gain bu ffer bypassed, 2v p-p, 1 rxpga gain low power mode 2, buffer enabled, 1v p-p input, 2 rxpga gain bu ffer enabled, 1v p-p input, 2 rxpga gain tpc 15. ad9862 rx sinad vs. f in at 16 msps f in e mhz 0 200 50 sinad e dbc 52 50 48 46 44 54 150 250 100 56 58 60 62 300 low power mode 2, buffer bypassed, 2v p-p input, 1 rxpga gain bu ffer bypassed, 2v p-p, 1 rxpga gain low power mode 2, buff er enabled, 1v p-p input, 2 rxpga gain bu ffer enabled, 1v p-p input, 2 rxpga gain tpc 18. ad9860 rx sinad vs. f in at 16 msps
rev. 0 ad9860/ad9862 ?11? input frequency e mhz 0 100 10 1000 thd e dbc e60 e65 e70 e75 e80 e85 e90 e50 e55 e95 e100 bu ffered bypass 2v input, 1 gain bu ffered 2v input, 1 gain bu ffered 1v input, 2 gain bu ffered bypass 1v input, 2 gain tpc 19. rx thd vs. f in , f adc = 64 msps input frequency e mhz 0 sfdr e dbc 100 e60 e65 e70 e75 e80 e85 e90 10 1000 e50 e55 e95 e100 bu ffered bypass 1v input, 2 gain bu ffered bypass 2v input, 1 gain bu ffered 1v input, 2 gain bu ffered 2v input, 1 gain tpc 22. rx sfdr @ 64 msps input frequency e mhz 1 relative attenuation e db 1 0 e1 e2 e3 e4 e5 e6 10 100 1000 no buff 2v 1 bu ff 1v 2 bu ff 2v 1 tpc 25. rx input attenuation f in e mhz 0 200 50 thd e dbc e75 e80 e85 e90 e70 150 250 100 e65 e60 e55 e50 300 ad9860 low power mode 1, buffer enabled, 1v p-p input, 2 rxpga gain ad9862 low power mode 1, buffer enabled , 1v p-p input, 2 rxpga gain ad9860 low power mode 1, bu ffer bypassed, 2v p-p input, 1 rxpga gain ad9862 low power mode 1, bu ffer bypassed, 2v p-p input, 1 rxpga gain tpc 20. rx thd vs. f in , f adc = 32 msps f in e mhz 0 200 50 sfdr e dbc e75 e80 e85 e90 e70 150 250 100 e65 e60 e55 e50 300 e95 ad9862 low power mode 1, bu ffer bypassed, 2v p-p input, 1 rxpga gain ad9860 low power mode 1, bu ffer bypassed, 2v p-p input, 1 rxpga gain ad9862 low power mode 1, bu ffer enabled , 1v p-p input, 2 rxpga gain ad9860 low power mode 1, bu ffer enabled, 1v p-p input, 2 rxpga gain tpc 23. rx sfdr @ 32 msps f in e mhz 0 input impedance e 60 250 240 230 220 210 200 190 20 40 80 100 270 260 180 280 tpc 26. rx input buffer impedance vs. f in f in e mhz 0 200 50 thd e dbc e75 e80 e85 e90 e70 150 250 100 e65 e60 e55 e50 300 ad9860 low power mode 2, buffer enabled, 1v p-p input, 2 rxpga gain ad9860 low power mode 2, bu ffer bypassed, 2vp-p input, 1 rxpga gain ad9862 low power mode 2, bu ffer bypassed, 2v p-p input, 1 rxpga gain ad9862 low power mode 2, bu ffer enabled , 1v p-p input, 2 rxpga gain tpc 21. rx thd vs. f in , f adc = 16 msps f in e mhz 0 200 50 sfdr e dbc e75 e80 e85 e90 e70 150 250 100 e65 e60 e55 e50 300 e95 ad9862 low power mode 2, bu ffer enabled , 1v p-p input, 2 rxpga gain ad9860 low power mode 2, bu ffer bypassed, 1v p-p input, 2 rxpga gain ad9860 low power mode 2, bu ffer enabled, 1v p-p input, 2 rxpga gain ad9862 low power mode 2, buffer bypassed, 2v p-p input, 1 rxpga gain tpc 24. rx sfdr @ 16 msps f adc e msps 040 10 rx analog power e mw 300 200 100 0 400 30 50 20 500 600 700 800 70 nominal 32msps lp mode 16msps lp mode 60 tpc 27. rx analog power consumption
rev. 0 ?12? ad9860/ad9862 register map (0x00e0x3f) 1 register name address 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 general 0 sdio bidir lsb first soft reset rx power down 1 v ref (diff) v ref rx digital rx channel b rx channel a buffer b buffer a all rx rx a2 byp buffer a rxpga a rx b3 byp buffer b rxpga b rx misc 4 hs duty cycle shared ref clk duty rx i/f 5 three state rx retime twos inv rxsync mux out complement rx digital 6 2 channel keep C C C
rev. 0 ad9860/ad9862 ?13? register bit definitions register 0: general bit 7: sdio bidir (bidirectional) default setting is low, which indicates spi serial port uses dedi- cated input and output lines (i.e., 4-wire interface), sdio and sdo pins, respectively. setting this bit high configures the serial port to use the sdio pin as a bidirectional data pin. bit 6: lsb first default setting is low, which indicates msb first spi port access mode. setting this bit high configures the spi port access to lsb first mode. bit 5: soft reset writing a high to this register resets all the registers to their default values and forces the dll to relock to the input clock. the soft reset bit is a one shot register and is cleared immediately after the register write is completed. register 1: rx pwrdwn bit 7: v ref , diff (power-down) setting this bit high will power down the adc
rev. 0 ?14? ad9860/ad9862 setting this bit high enables the decimation filters and decimates the receive data by two. register 8: tx pwrdwn bit 5: alt timing mode the timing section in the data sheet describes two timing modes, the 12% i outfs (2.4 ma for a 20 ma full- scale output) can be applied to either differential pin on each channel. the offset current can be used to compensate for offsets that are present in an external mixer stage, reducing lo leakage at its output. default setting is hex00, no offset current. the offset current magnitude is set using the lower nine bits. setting the msb high will add the offset current to the selected differen- tial pin, while an msb low setting will subtract the offset value. dac a/dac b offset direction this bit determines to which of the differential output pins for the selected channel the offset current will be applied. setting this bit low will apply the offset to the negative differential pin. setting this bit high will apply the offset to the positive differential pin. register 14/15: dac gain a/b bit 6, 7: dac a/dac b coarse gain control these register bits will scale the full-scale output current (i outfs ) of either tx channel independently. i out of the tx channels is a function of the r set resistor, the txpga setting, and the coarse gain control setting. msb, lsb tx channel current scaling 10 or 11 does not scale output current 01 scales output current by 1/2 00 scales output current by 1/11 bit 5e0: dac a/dac b fine gain the dac output curve can be adjusted fractionally through the gain trim control. gain trim of up to 4% can be achieved on each channel individually. the gain trim register bits are a twos complement attention control word. msb, lsb 100000 maximum positive gain adjustment 111111 minimum positive gain adjustment 000000 no adjustment (default) 000001 minimum negative gain adjustment 011111 maximum negative gain adjustment register 16: txpga gain bit 0e7: txpga gain this 8 bit, straight binary (bit 0 is the lsb, bit 7 is the msb) reg- ister controls for the tx programmable gain amplifier (txpga). t he txpga provides a 20 db continuous gain range with 0.1 db steps (linear in db) simultaneously to both tx channels. by default, this register setting is hex00. msb, lsb 000000 minimum gain scaling C
rev. 0 ad9860/ad9862 ?15? bit 5: q/i order this register indicates the order of received complex transmit data. by default this bit is low, representing i data preceding q data. alternatively, if this bit is set high, the data format is defined as q data preceding i data. bit 4: inv txsync this register identifies how the first and second data sets are identified in a complex data set using the txsync bit. by default this bit is low, and txsync low indicates the first data set is at the tx port; txsync high indicates the second data set is at the tx port. setting this bit high inverts the txsync bit. txsync high indicates the first of the data set, and txsync low indicates the second of the data set. bit 3: twos complement the default data format for tx data is straight binary. set this bit high when providing twos complement tx data. bit 2: inverse sample by default, the transmit data is sampled on the rising edge of the clkout. setting this bit high will change this, and the transmit data will be sampled on the falling edge. bit 1: 2 edges if the clkout rate is running at half the interleaved data rate, both edges of the clkout must latch transmit data. setting this bit high allows this clocking configuration. bit 0: interleaved by default, the ad9860/ad9862 powers up in single dac operation. if dual transmit data is to be used, the interleaved data option needs to be enabled by setting this bit high. register 19: tx digital bit 4: 2 data paths setting this bit high enables both transmit digital paths. by default, this bit is low and the transmit path utilizes only a single channel. bit 3: keep eve this bit configures the tx hilbert filter for either positive or nega- tive frequencies pass band, assuming it is enabled. by default this bit is low, which selects the positive frequencies. setting this bit high will setup the hilbert filter to pass negative frequencies. bit 2: hilbert this bit enables or disables the hilbert filter in the transmit path. by default, this bit is low, which disables the transmit hilbert filter. setting this bit high enables the transmit hilbert filter. bit 1,0: interpolation control these register bits control the interpolation rate of the transmit path. default settings are both bits low, indicating that both inter- polation filters are bypassed. the msb and lsb are address d19, bits 1 and 0, respectively. setting binary 01 provides an interpo- lation rate of 2 ; binary 10 provides an interpolation rate of 4 . register 20: tx modulator bit 5: negative fine tune when this bit is low (default), the numerically controlled oscil- lator ( nco) provides positive shifts in frequency, assuming fine modulation is enabled. setting this bit high will use a negative frequency shift in the fine complex modulator. bit 4: fine mode by default, the nco and fine modulation stage are bypassed. setting this bit high will enable the use of the digital complex modulator, enabling tuning with the nco. bit 3: real mix mode this bit determines if the coarse modulation (controlled by register coarse modulation, will perform a separate real mix on each channel or a complex mix using the dual channel data. by default, this bit is set low and a complex mix will be performed. setting this bit high will enable the real mix mode. note, the fine modulator block only performs complex mixing. bit 2: negative coarse tune when this bit is low (default), the coarse modulator provides positive shifts in frequency. setting this bit high will shift the coarse modulator processed data negative in frequency. bit 1,0: coarse modulation these bits control what coarse modulation processing will be performed on the transmit data. a setting of binary 00 (default) will bypass the modulation block, a setting of binary 01 will shift the transmit data by f dac /4, and a setting of binary 10 will shift the transmit data by f dac /8. register 21/22/23: nco tuning word ftw [23:0] these three registers set the 24-bit frequency tuning word (ftw) for the nco in the fine modulator stage of the tx path. the nco full-scale tuning word is straight binary and produces a frequency equivalent to f dac /4 with a resolution of f dac /2 26 . register 24: dll bit 6: input clock control this bit defines what type of clock will be driving the ad9860/ ad9862. the default state is low, which allows either crystal con- nected to osc1 and osc2 or single-ended reference clock driving osc1 to drive the internal timing circuits. if a crystal will not be used, the internal oscillator should be disabled after power-up by setting this bit high. bit 5: adc div2 by default, the adc is driven directly by the input clock in normal timing operation mode or the dll output in the alternative timing operation mode. setting this bit high will clock the adc at one half the previous clock rate. this is described further in the timing section. bit 4,3: dll multiplier these bits control the dll multiplication factor. a setting of binary 00 will bypass the dll, a setting of binary 01 will multiply the input clock by 2, and a setting of binary 10 will multiply the input clock by 4. default mode is defined by mode/txblank logic level at power-up or reset, which configures either normal operation timing mode or alternative timing mode. in alter- native timing mode, the dll will lock to 4 multiplication factor (the dll fast register remains low by default). if the mode/txblank pin is low, by default the dll will be bypassed and a 1 clock is used internally. bit 2: dll power-down setting this register bit high forces the clk in multiplier to a power-down state. this mode can be used to conserve power or to bypass the internal dll. to operate the ad9860/ad9862 when the dll is bypassed, an external clock equal to the fastest on-chip clock is supplied to the osc pin(s). bit 0: dll fast the dll can be used to generate output frequencies between 32 mhz to 128 mhz. because of the large range of locking fre- quencies allowed, the dll is separated into two output frequency ranges, a
rev. 0 ?16? ad9860/ad9862 default, this bit is low, setting up the dll in
rev. 0 ad9860/ad9862 ?17? blank registers blank registers, i.e., the registers with 0 settings and no indicated function, are placeholders used throughout the register map for spacing the ad9860/ad9862 control bits in a logic fashion and, potentially can be used for future development. a low should always be written to these registers if a write needs to take place. serial port interface the serial port interface (spi) is used to write to and read from the ad9860/ad9862 internal programmable registers. the serial interface uses four pins: sen, sclk, sdio, and sdo by default. sen is a serial port enable pin, sclk is the serial clock pin, sdio is a bidirectional data line and sdo is a serial output pin. sen is an active low control gating read and write cycles. when sen is high, sdo and sdio are three-stated. sclk is used to synchronize spi read and writes at a maximum bit rate of 16 mhz. input data is registered on the rising edge and output data transitions on the falling edge. during write opera- tions, the registers are updated after the 16th rising clock edge (and 24th rising clock edge for the dual byte case). incomplete write operations are ignored. sdio is an input only by default. optionally, a 3-pin interface may be configured using the sdio for both input and output opera- tions and three-stating the sdo pin (see sdio bidir register). sdo is a serial output pin used for read back operations in 4-wire mode and is three-stated when sdio is configured for bidirectional operation. instruction header each spi read or write consists of an instruction header and data. the instruction header is made up of an 8-bit word and is used to set up the register data transfer. the 8-bit word consists of a read/not write bit, r/nw (the msb), followed by a double/ not single bit (2/n1) and the 6-bit register address. write operations the spi write operation uses the instruction header to configure a one or two register write using the 2/n1 bit. the instruction byte followed by the register data, is written serially into the device through the sdio pin on rising edges of the interface clock at sclk. the data can be transferred msb first or lsb first depending on the setting of the lsb first register. figure 1 includes a few examples of writing data into the device. figure 1a shows a write using 1 byte and msb first mode set; figure 1b shows an msb first, 2 byte write; and figure 1c shows an lsb first, 2 byte write. note the differences between lsb and msb first modes: instruction header and data are reversed, and in 2 byte writes, the first data byte is written to the address in the header, n and the second data byte is written to the n C
rev. 0 ?18? ad9860/ad9862 read operation the read back of registers is a single data byte operation. the readback can be configured to use three pins or four pins and can be formatted as msb first or lsb first. the instruction header is written to the device either msb or lsb first (depending on the mode) followed by the 8-bit output data (appropriately msb or lsb justified). by default, the output data is sent to the dedicated output pin (sdo). 3-wire operation can be configured by set- ting the sdio bidir register. in 3-wire mode, the sdio pin will become an output pin after receiving the 8-bit instruction header with a read back request. figure 2a shows an msb first, 4-pin spi read; figure 2b shows an msb first, 3-pin read; and figure 2c shows an lsb first, 4-pin read. system block description the ad9860/ad9862 integrates transmit and receive paths with digital signal processing blocks and auxiliary features. the auxiliary sdio sen sclk t s t ds t dh t lo t hi t clk t h instruction header (register n) sdo sdio sen sclk sdio sen sclk sdo t dv don?t care don?t care don?t care don?t care don?t care don?t care r/nw 2/n1 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 output register data t s t ds t dh t lo t hi t clk t dv t h don?t care don?t care r/nw 2/n1 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 don?t care don?t care output register data instruction header t s t ds t dh t lo t hi t clk t dv t h don?t care r/nw 2/n1 don?t care don?t care don?t care don?t care don?t care a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 output register data instruction header figure 2. spi read examples a. (top) 4-wire interface, msb first; b. (middle) 3-wire interface, msb first; c. (bottom) 4-wire interface, lsb first features include two auxiliary adcs, a programmable sigma-delta output, three auxiliary dacs, integrated clock circuitry to generate all internal clocks, and buffered output clocks from a single input reference. the ad9860/ad9862 system functionality is described in the following four sections: the transmit block, receive block, timing generation block, and the auxiliary function block. the following sections provide a brief description of the blocks and applications for the four sections. transmit section components the transmit block (tx) accepts and can process real or complex data. the tx interface is configurable for a variety of data formats and has special processing options such as interpolation and hilbert filters. a detailed block diagram of the ad9860/ad9862 transmit path is shown in figure 3. the transmit block diagram is broken into these stages: dac (block a), c oarse mod ulation (block b),
rev. 0 ad9860/ad9862 ?19? interpolation stage (block c), fine modulation stage (block d), hilbert filter (block e), and the latch/demultiplexing circuitry. dac the dac stage of the ad9860/ad9862 integrates a high perfor- mance tx dac core, a programmable gain control through a programmable gain amplifier (txpga), coarse gain control, and offset adjustment and fine gain control to compensate for system mismatches. the txdac core of the ad9860/ad9862 provides dual, differen- tial, complementary current outputs generated from the 12-/14-bit data. the 12-/14-bit dual dacs support update rates up to 128 msps. the differential outputs (i.e., iout+ and iout C i outfsmax , is set by the external resistor (r set ), which sets the dac reference current. the r set resistor is connected between the fsadj pin to ground. the relationship between i outfsmax and r set is: i outfsmax set v r ~ . 67 123 ? ? ? typically, r set is 4 k w , which sets i outfsmax to 20 ma, the optimal dynamic setting for the txdacs. increasing r set by a factor of 2 will proportionally decrease i outfsmax by a factor of 2. i outfsmax of each dac can be re-scaled either simulta- neously with the txpga gain register or independently with dac a/b coarse gain registers. the txpga function provides 20 db of simultaneous gain range for both dacs and is controlled by writing to spi register txpga gain for a programmable full-scale output of 10% to 100% i outfsmax . the gain curve is linear in db, with steps of about 0.1 db. internally, the gain is controlled by changing the main dac bias currents with an internal txpga dac whose output is heavily filtered via an on-chip r-c filter to provide continuous gain transitions. note, the settling time and band- width of the txpga dac can be improved by a factor of 2 by writing to the txpga fast register. each dac has independent coarse gain control. coarse gain control can be used to accommodate different i outfs from the dual dacs. the coarse full-scale output control can be adjusted using the dac a/b coarse gain registers to 1/2 or 1/11th of the nominal full scale current. fine gain controls and dc offset controls can be used to compen- sate for mismatches (for system level calibration), allowing improved matching characteristics of the two tx channels and aiding in suppres- sing lo feedthrough. this is especially useful in image rejection architectures. the 10-bit dc offset control of each dac can be used independently to provide a 12% i outfsmax of offset to either differential pin, thus allowing calibration of any system offsets. the fine gain control with 5-bit resolution allows the i outfsmax of each dac to be varied over a 4% range, thus allowing compensation of any dac or system gain mismatches. fine gain control is set through the dac a/b fine gain registers and the offset control of each dac is accomplished using dac a/b offset registers. a power-down option allows the user to power down the analog supply current to both dacs or either dac, individually. a digital power-down is also possible through either the tx pwrdwn register or the mode/txblank pin. coarse modulator a digital coarse modulator is available in the transmit path to shift the spectrum of the input data by f dac /4 or f dac /8. if the input data consists of complex data, the modulator can be con- figured to perform a complex modulation of the input spectrum. if the data in the transmit path is not complex, a real mix can be performed separately on each channel thereby frequency shifting the real data and images by f dac /4 or f dac /8. real or complex mixing is configured by setting the real mix register. by default, the coarse modulator is bypassed. it can be configured using coarse modulation and neg coarse tune registers. interpolation stage interpolation filters are available for use in the ad9860/ad9862 transmit path, providing 1 (bypassed), 2 , or 4 interpolation. the interpolation filters effectively increase the tx data rate while suppressing the original images. the interpolation filters digitally shift the worst case image further away from the desired signal, thus reducing the requirements on the analog output reconstruc- tion filter. there are two 2 interpolation filters available in the tx path. an interpolation rate of 4 is achieved using both interpolation filters; an interpolation rate of 2 is achieved by enabling only the first 2 interpolation filter. the first interpolation filter provides 2 interpolation using a 39 tap filter. it suppresses out-of-band signals by 60 db or more and has a flat passband response (less than 0.1 db ripple) extend- ing to 38% of the ad9860/ad9862 input tx data rate (19% of the dac update rate, f dac ). the maximum input data rate is 64 msps per channel when using 2 interpolation. tx dac bypassable digital qu adrature mixer pga iout+a ioutea tx dac pga iout+b iouteb hilbert filter block a block b block c block d block e hilbert filter dds bypassable low-pass interpolation filter bypassable digital qu adrature mixer f s /4, f s /8 dac i q txdata [0:13] figure 3. transmit section block diagram
rev. 0 ?20? ad9860/ad9862 the second interpolation filter will provide an additional 2 inter- polation for an overall 4 interpolation. the second filter is a 15 tap filter. it suppresses out-of-band signals by 60 db or more. the flat passband response (less than 0.1 db attenuation) is 38% of the tx input data rate (9.5% of f dac ). the maximum input data rate per channel is 32 msps per channel when using 4 interpolation. the 2 and 4 interpolation filter transfer function plots are shown in figure 4a and 4b, respectively. normalized e f s 10 0 magnitude e db 0 e10 e20 e30 e40 e50 e60 e70 e80 e100 0.1 e90 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 interpolation filter includung sin (x)/x normalized e f s 10 0 magnitude e db 0 e10 e20 e30 e40 e50 e60 e70 e80 e100 0.1 e90 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 interpolation filter includung sin (x)/x figure 4. spectral response of 2 interpolation filter (top) and 4 interpolation filter (bottom) fine modulation stage a digital fine modulation stage is available in the transmit path to shift the complex tx output spectrum using a 24-bit numerically controlled oscillator (nco). to utilize the fine modulation block, 4 interpolation is required. therefore, the maximum input date rate is 32 msps per channel, which generates a dac update rate, f dac , of 128 msps. the nco can tune up to 1/4 of f dac , providing a step resolution of f dac /2 26 . since the fine modulation stage precedes the interpolation filters, care must be taken to ensure the entire desired signal is placed within the pass band of the interpolation filter. by default, the fine modulation block is bypassed. to enable it to perform a complex mix of the tx i and q data, register 2
rev. 0 ad9860/ad9862 ?21? in most systems, the dac (and each up-converter stage) requires analog filtering to meet spectral mask and out-of-band spurious emissions requirements. digital interpolation (block c) and hilbert filtering (block e) can be used to relax some of the system analog filtering. digital 2 interpolation with input data rates of up to 64 msps or 4 interpolation with input data rates of 32 msps is available in this mode (or interpolation filters can be bypassed to achieve a 128 msps input data rate). the data bandwidth with 2 or 4 interpolation enabled is up to 38% of the input data rate. if no interpolation is enabled, the data bandwidth will be the full nyquist band with sinc limitations. the interpolation filters are configured through the interpolation serial register. the hilbert filter can be enabled in this mode to suppress the positive or negative image that naturally occurs with real data. the single sideband signal when combined with a quadrature modulator can upconvert the desired signal and suppressed image, forming a hartley image rejection architecture (both tx paths need to be enabled to produce the image rejection architecture). the hilbert filter will provide over 50 db image suppression for signals between 12.5% to 38% of the input data rate. the hil- bert filter can be enabled and configured using the hilbert and keep C C C 68% of the dac nyquist frequency. if all tx dsp blocks are bypassed, the ad9860/ad9862 oper- ates similar to a standard txdac. in single channel dac data mode, only the channel a dac is used; channel b is powered down to reduce power consumption. two independent real signal dac data the dual channel real dac data mode is used to transmit diversity or dual channel signals. in this mode, 12-/14-bit, dual channel, interleaved tx data is provided to the ad9860/ad9862 and latched using either clkout1 or clkout2 edges as defined in the clock overview section of the data sheet. both tx paths are enabled and the two signals will be processed independently. the tx digital processing blocks available in this mode are the interpolation filters (block c) and the coarse modulator (block d). as mentioned previously, the interpolation filters can be used to relax requirements on the external analog filters. the maximum rate of the tx interface is 128 msps, i.e., 64 msps/channel with interleaved data. therefore to fully take advantage of the dacs maximum update rate of 128 msps, 2 interpolation is required. the 4 interpolation filter is recommended for input data rates equal to or less than 32 msps/channel (64 msps interleaved). the data bandwidth with 2 or 4 interpolation enabled is up to 37.5% of the channel input data rate. if no interpolation is enabled, the data bandwidth will be the full nyquist band with sinc limitations. the interpolation filters are configured through the interpolation serial register. the coarse modulation will perform a real mix of each channel, independently, with either f dac /4 or f dac /8. dual channel complex dac data the dual channel complex dac data (also known as single sideband data) is used to generate complex tx signals (i.e., i and q). in this mode, 12-/14-bit, interleaved i and q data is provided to the ad9860/ad9862 and latched using either clkout1 or clkout2 edges as defined in the clock overview section of the data sheet. both tx paths are enabled and the two signals will be processed as a complex waveform. the tx digital pro- cessing blocks available in this mode are the fine modulator (block b), the interpolation filters (block c), and the coarse modulator (block d). as mentioned previously, the interpolation filters can be used to relax requirements on the external analog filters. the maximum rate of the tx interface is 128 msps, i.e., 64 msps/channel with interleaved data (as is the case in this mode). therefore, to fully take advantage of the dac C C 70% of the dac nyquist frequency.
rev. 0 ?22? ad9860/ad9862 receive section components the receive block is configurable to process input signals of dif- ferent formats and has special features such as an input buffer, gain stage, and decimation filters. the ad9860/ad9862 receive path block diagram is shown in figure 6. the block diagram can be broken into the following stages: input buffer (block a), rxpga (block b), dual, 10-/12-bit, 64 msps adc (block c), decimation filter (block d), digital hilbert block (block e), and a data output multiplexer. the function of each stage is explained in the following paragraphs. input buffer stage the input buffer stage buffers the input signal on-chip for both receive paths. the buffer stage has two main benefits, providing a constant input impedance and reducing any w impedance over the entire input signal range. the constant input impedance accommodates matching networks to ensure proper transfer of signal to the input of the device. the input buffer is self-biased to ~ 2 v, and therefore the input signal should be ac-coupled to the rx differential input or have a common-mode voltage of about 2 v. if an external buffer is present, the internal input buffer can be bypassed and powered down to reduce power consumption. the input buffer accepts up to a 2 v p-p input signal for maximum snr performance. optimal thd perfor- mance occurs with 1 v p-p input signal. for if sampling, the input buffer can be used with input signals up to about 100 mhz, the 3 db bandwidth of the buffer. when undersampling the input signal, the output spectrum will contain an aliased version of the original, higher frequency signal. as was the case with nyquist sampling, the input signal should be ac-coupled to the rx differential input or have a common-mode voltage of ~ 2 v. for input signals over 100 mhz to about 250 mhz, the input buffer needs to be bypassed and an external input buffer is required. in the case that the input buffer is bypassed, the input circuit is a switched capacitor network. the switching input impedance during the sample phase is about 1/(2( )fc), where f is the input frequency and c is the input capacitance (about 4 pf). during hold mode, the input impedance is > 1 m w . rxpga the rxpga stage has a programmable gain amplifier that can be used to amplify the input signal to utilize the entire input range of the adc. the rxpga stage provides a 0 db to 20 db gain range in steps of about 1 db. the rx channel independent gain control is accomplished through two 5-bit spi programmable rxpga a/b registers. the gain curve is linear in db with a minimum gain setting (0 db, nominally) of hex00 and a maximum gain setting (20 db, nominally) of hex14. the rxpga stage can provide up to a 2 v p-p signal to the adc input. analog-to-digital (a/d) converter the analog-to-digital converter (adc) stage consists of two high performance 10-/12-bit, 64 msps analog-to-digital (a/d) converters. the dual a/d converter paths are fully independent, except for a shared internal bandgap reference source, v ref . each of the a/d converter m f and a 0.1 m f capacitor in parallel to ground. separate top and bottom references, v rt and v rb , for each converter are generated from v ref and should also be decoupled. recommended decoupling for the top and bottom references consists of using 10 m f and 0.1 m f capacitors in parallel between the differential reference pins, and a 0.1 m f capacitor adc low-pass decimation filter pga 1 vin+a vinea adc pga 1 vin+b vineb hilbert filter block a block b block c block d block e rxa data [0:11] rxb data [0:11] figure 6. receive section block diagram
rev. 0 ad9860/ad9862 ?23? from each to ground. the internal references can also be disabled (powered down) and driven externally to provide a different input voltage range or low drift reference. if an external v ref reference is used, it should not exceed 1.0 v. a shared reference mode allows the user to connect the differen- tial references from both adcs together externally for superior gain matching performance. if the adcs are to function inde- pendently, then the reference can be left separate and will provide superior isolation between the dual channels. shared reference mode can be enabled through the shared ref register. a power-down option allows the user to power down both adcs (sleep mode) or either adc individually to reduce power con sumption. decimation stage for signals with maximum frequencies less than or equal to 3/16 the adc sampling rate, f adc , the decimate by 2 filter (or half-band filter) can be used to provide on-chip suppression of out-of- band images and noise. when data is present in frequencies greater than 1/4 f adc , the decimate by 2 filter can be disabled by switching the filter out of the circuit. the decimation filter allows the adc to oversample the input while decreasing the output data rate by half. the two main benefits are a simplification of the input anti- aliasing filter and a slower data interface rate with the external digital asic. the decimation filter is an 11 tap filter and suppresses out of band noise by 38 db. hilbert block the hilbert filter is available to provide a hilbert transform of the data from the adc in channel b. the digital hilbert transform, in combination with an external complex downconverter, enables a receive image rejection architecture (similar to hartley image rejection architecture). the hilbert filter pass-band (< 0.1 db ripple) is between 25% to 75% of the nyquist rate of its input data rate. the maximum data rate of the rx hilbert filter is 32 msps. at adc rates higher than this, the decimation filters should be enabled. the hilbert filter transfer function plots are shown in figure 7. normalized e f s e40 e0.5 magnitude e db e80 e120 e0.4 e0.3 e0.2 e0.1 0 0.1 0.2 0.3 0.4 0.5 0 figure 7. rx hilbert filter, keeping positive frequencies response data output multiplexer stage the rx data output format can be configured for either twos c omplement or offset binary. this is controlled by the rx twos complement register. the output data from the dual adcs can be multiplexed onto a single 10-/12-bit output bus. the multiplexing is synchronized using the rxsync output pin that indicates which channel data is on the output bus. receive applications section the ad9860/ad9862 receive path (rx) includes two high speed, high performance, 10-/12-bit adcs. figure 6 shows a detailed block diagram of the rx data path and can be referred to through- out the explanation of the various modes of operation. the various rx modes of operation are broken into three parts determined by the type of input signal: 1. single channel adc signal 2. dual channel real adc signal (diversity or dual channel) 3. dual channel complex adc signal (i and q or single sideband). each one of these parts is further divided into two cases, sampling input signals up to nyquist of the adc (nyquist sampling) and sampling at rates above adc nyquist rate (if sampling or undersampling). the ad9860/ad9862 uses oversampling and decimation filters to ease requirements on external filtering components. the decima- tion filters (for both receive paths) can be used or bypassed so as to accommodate different signal bandwidths and provide different output data rates to allow easy integration with several different data processing schemes. nonbaseband data can be used in an effort to avoid the dc offsets in the receive signal path that can cause errors. by receiving nonbaseband data, the requirements of external filtering may be greatly reduced. in each of the different receive modes, the input buffer, program- mable g ain amplifier (rxpga), and output multiplexer remain within the receive path. single channel adc signal in this mode, a single input signal to be digitized is connected to the differential input pins, vin+a and vin C C C
rev. 0 ?24? ad9860/ad9862 the output will be latched using some configuration of clkout1 or clkout2 edges as defined in the clock overview section of the data sheet. the rx path available options include bypassing the input buffer, rxpga control and using the decimation filter. the input buffer description above explains the conditions under which the buffer should be bypassed. if the input signal, or the undersampled alias signal for the if sampling case, falls below 40% of the adc nyquist rate, the decimation filter can be enabled to suppress out-of-band noise and spurious signals by 40 db or more. with the decimation filter enabled the snr of the rx path improves by about 2.3 db. dual channel complex adc signal the dual channel complex adc signal mode is used to receive baseband i and q signals or a single sideband signal at some if. in this mode, a complex input signal is generated from an external quadrature demodulator. the in-phase channel (i channel) is connected to vin+a and vin C C w ). an internal delay lock loop (dll) based clock multiplier pro- vides a low noise, 2 or 4 multiplication of the input clock over an output frequency range of 32 mhz to 128 mhz. the dll fast register should be used to optimize the dll performance. for dll output frequencies between 32 mhz and 64 mhz, this bit should be set low. for output frequencies between 64 mhz to 128 mhz, the fast bit should be set high (for a 64 mhz out- put frequency, the register can be set either high or low). the dll can be bypassed by setting a 1 multiplication factor in the dll multiplier register. the dll can be powered down when it is bypassed for power savings by setting the dll pwrdwn register. for applications where an external crystal is desired, the ad9860/ ad9862 internal oscillator circuit and the dll clock multiplier enable a low frequency, lower cost quartz crystal to be used to generate the input reference clock. the quartz crystal would be connected between the osc1 and osc2 pins with parallel resonant load capacitors as specified by the crystal manufacturer. an internal duty cycle stabilizer (dcs) can be enabled on the ad9860 by setting the clk duty register. this provides a stable 50% duty cycle to the adc for high speed clock rates between 40 msps to 64 msps when proper duty cycle is more critical. system clock distribution circuitry there are many variables involved in the timing distribution. external variables include clkin, clkout1, clkout2, rx data rate, tx data rate. internal variables include adc conversion rate, dac update rate, interpolation rate, decimation rate, rx data multiplexing and tx data demultiplexing. many of these parameters are interrelated and based on clkin. optimal power versus performance and ease of integration options can be chosen to suit a particular application. adc data mux and latch data latch and demux no decimation, 2 decimate: reg d6 b0 mux out: reg d5 b0 rx retime: reg d5 b3 2 data paths: reg d19 b4 q/i order: reg d18 b5 tx retime: reg d18 b6 no interp 2, 4 interpolation: reg d19 b0, 1 div inv no inversion, invert inv1: reg d25 b1 1 , 1/2 clksel 1 , 1/2 adc div2: reg d24 b5 dll multiplier: reg d24 b3, 4 div inv dll div 1 , 1/2 , 1/4 no inversion, invert inv2: reg d25 b5 1 , 2 , 4 clkout2 div factor: reg 25 b6, 7 dac clock path data path clkin rx data [0:23] clkout1 clkout2 tx data [0:13] figure 8. normal operation timing block diagram one of two possible timing operation modes can be selected. the typical timing mode is called normal operation mode; a block diagram is shown in figure 8. the other mode is called alterna- tive operation mode, and a block diagram is shown in figure 12.
rev. 0 ad9860/ad9862 ?25? t r 1 t r 3 t r 2 t r 1 f clkout1 rx data timing no. 1 f rx = clkout 4 rx data timing no. 2 f rx = clkout 2 rx data timing no. 3 f rx = clkout rx data timing no. 4 f rx = 2 clkout figure 9. rx timing diagram 0: b = a 1: b = a/2 00: c = b 01: c = b/2 10: c = b/4 00: e = d 01: e = 2 d 10: e = 4 d adc sample rate (not to exceed 64mhz) dll output rate (not to exceed 128mhz) clkout2 input tx data rate (single channel) txdac update rate single channel (cannot exceed dll output rate) clkin ab de adc div2 dll mult interp 00: d = c 01: d = c/2 10: d = c/4 c clkout2 div figure 10. single tx timing block diagram, alternative operation table i. rx data timing table table ia. clksel set logic low adc see figure 8 for clksel div 2 decimate multiplex relative timing timing no. 4 no mu x rx data = 2 clkout1 clkout1 = 1 ? ? ? ? ? ? ? ? ? ? ? ?
rev. 0 ?26? ad9860/ad9862 for the normal operation mode, the tx timing is based on a clock derived from the dll output, while the rx clock is unaffected by the dll setting. the alternative operation mode, timing utilizes the output of the dll to generate both rx and tx clocks. it also sets default operation of the dll to 4 mode. normal operation is typically recommended because the rx adc is more sensitive to the jitter and noise that the dll may gener- ate, so its performance may degrade. the mode/txblank pin logic level at power up or reset defines in which mode the device powers up. if mode/txblank is low at power up, the n orm al operation mode is configured. otherwise, the alternative operation m ode is configured. rx path (normal operation) the adc sampling rate, the rx data output rate, and the rate of clkout1 (clock used to latch output data) are the parameters of interest for the receive path data. these parameters in addition to the data bandwidth are related to clkin by decimation filters, divide by two circuits, data multiplexer logic and retiming latches. the rx path timing can be broken into two separate relation- ships: the adc sample rate relative to the input clock, clkin and the output data rate relative to clkout1. the adcs sample rate relative to clkin is controlled by the adc div2 register and the sample rate can be equal to or one half of the input clock rate. the output data relative to clkout1 has many configurations providing a flexible interface. the different options are shown in figure 8. table ia and ib describe the setup required to obtain the desired data timing. rxsync is available when the rx data is decimated and multiplexed to identify which channel data is present at the output bus. 00: c = b 01: c = 2 b 10: c = 4 b 00: d = c 01: d = c/2 10: d = c/4 00: g = f 01: g = 2 f 10: g = 4 f adc sample rate (not to exceed 64mhz) dll output rate (not to exceed 128mhz) clkout2 input tx data rate txdac update rate each channel (cannot exceed dll output rate) b eg dll mult clkout2 div interp 0: e = d 1: e = 2 d c 2 edges f = e/2 d dual channel fac t or input tx data rate each channel 0: b = a 1: b = a/2 clkin a adc div2 f figure 11. dual tx timing block diagram, alternative operation tx data timing no. 1 f tx = clkout2 tx data timing no. 2 f tx = 2 clkout2 f t 1 f t 3 f t 2 f t 4 f clkout2 figure 12. tx timing diagram the rx data (unless re-timed using the rx retime register) is timed relative to the clkout1 pin output. the rx output data can be decimated (halving the data rate) or both channels can be multiplexed onto the channel a data bus (doubling the data rate). decimation enables oversampling while maintaining a slower external data transfer rate and provides superior suppression of out of band signals and noise. multiplexing enables fewer digital output bits to be used to transfer data from the rx path to the digital asic collecting the data. when mux mode is enabled with an output data rate equal to clkout1 (timing no. 3 in figure 9) then the rxsync pin is required to identify which channel
rev. 0 ad9860/ad9862 ?27? tx path (normal operation) the dac update rate, the tx input data rate, and the rate of clkout2 (clock used to latch tx input data) are the parameters of interest for the transmit path data. these parameters, in addition to the output signal bandwidth, are related to clkin by the settings of the adc div2, the dll multiplier, the clkout2 div, the two edges, and the interpolation registers. the tx data is timed relative to the clkout2 pin (unless it is retimed relative to clkout1 by setting tx retime register) and the input tx data is latched on either each rising edge, each falling edge or both edges (controlled through the inverse sample and two edges registers). the timing diagrams for these cases are shown in figure 12. the dual tx data is multiplexed onto a single bus so that fewer digital bits are necessary to transfer data. throughout this discus- sion of tx path timing, tx digital processing options other than interpolation are ignored because they do not change data timing; tx data timing reflects whether single or dual channel data is latched into the ad9860/ad9862. the rates of clkout2 (and the input data rate) are related to clkin by the dll multiplier register, the setting of the clkout2 divide factor register and the register adc div2. these relationships are shown in table ii. table ii. clkout2 timing relative to clkin for normal operation mode dll clkout2 clk div2 mult div factor clkout2 1 clkin 1 2clk in/2 4clk in/4 12 clkin no div 2 2 clkin 4clk in/2 14 clkin 4 22 clkin 4 clkin 1clk in/2 1 2clk in/4 4clk in/8 1 clkin div by 2 2 2clk in/2 4clk in/4 12 clkin 4 2 clkin 4clk in/2 adc data mux and latch data latch and demux no decimation, 2 decimate: reg d6 b0 mux out: reg d5 b0 rx retime: reg d5 b3 2 data paths: reg d19 b4 q/i order: reg d18 b5 tx retime: reg d18 b6 no interp, 2, 4 interpolation: reg d19 b0, 1 inv no inversion, invert inv1: reg d25 b1 inv div 1 , 1/2 , 1/4 no inversion, invert inv2: reg d25 b5 clkout2 div factor: reg 25 b6, 7 dac clkin rx data [0:23] clkout1 clkout2 tx data [0:13] dll multiplier: reg d24 b3, 4 dll 1 , 2 , 4 div 1 , 1/2 clksel 1 , 1/2 adc div2: reg d24 b5 div clock path data path figure 13. alternative operation timing block diagram
rev. 0 ?28? ad9860/ad9862 the timing block diagrams in figures 10 and 11 show how the various clocks of the single and dual tx path are affected by the various register settings. for dual tx data, an option to redirect demultiplexed data to either path is available. for example, the ad9860/ad9862 can accept complex data in the form of i then q data or q then i data, controlled through qi order register. for the dual tx data cases, the tx_sync pin input logic level defines what data is currently on the tx data bus. by default, when tx_sync is low, channel a data (first of the set) should be on the data bus; if txsync is high, channel b data (or the second of the set) should be on the tx bus. this can be reversed be setting the inv txsync register. rx path (alternative timing operation) the adc sampling rate, the rx data output rate and the rate of clkout1 (clock used to latch output data) are the parameters of interest for the receive path data. these parameters, in addition to the data bandwidth, are related to clkin by decimation filters, divide by two circuits, data multiplexer logic retiming latches and also the dll multiplication setting (which is not the case for normal operation mode). this mode can be configured by default by forcing the tx_blank_in pin to a logic high level during power up. the rx path timing can be broken into two separate relationships: the adc sample rate relative to the input clock, clkin and the output data rate relative to clkout1. the adcs sample rate relative to clkin is controlled by the adc div2 register and the dll multiplier register. the sample rate can be equal to or one half of the dll output clock rate. the output data rate relative to clkout1 for the alternative operation mode has the same configuration options as in the normal operation mode. the different options are shown in figure 9. table ia. and ib. describe the setup required to obtain the desired data timing. the rx data (unless retimed using the rx retime register) is timed relative to the clkout1 pin output. the rx output data can be decimated (halving the data rate) or both channels can be multiplexed onto the channel a data bus (doubling the data rate). decimation enables oversampling while maintaining a slower external data transfer rate and provides superior suppression of out of band signals and noise. multiplexing enables fewer digital output bits to be used to transfer data from the rx path to the digital asic collecting the data. when multiplexing mode is enabled with an output data rate equal to clkout1 (timing no. 3 in figure 9), then the rxsync pin is required to identify which channel
rev. 0 ad9860/ad9862 ?29? table iv. normal operation mode master timing guide 2 c d a l l d t l u m c d a k c o l c e t a r e t a r a t a d c d a 1 ) s p s m ( c a d e t a d p u e t a r e t a r a t a d c a d l a u d 2 ) s p s m ( 1 t u o k l c2t2 u o k l c e d o m x u m - n o nede o m x u i c e d o n 2 y b i c e d i c e d o n2 y b i c e d 1 p r e t n i 2 p r e t n i 4 p r e t n i l e s k l c w o l = l e s k l c h g i h = v i d k l c 1 = v i d k l c 2 ? ? ? ? ? ?
rev. 0 ?30? ad9860/ad9862 the timing block diagrams in figures 14 and 15 show how the various clocks of the single and dual tx path are affected by the various register settings. for dual tx data, an option to redirect demultiplexed data to either path is available. for example, the ad9860/ad9862 can accept complex data in the form of i then q data or q then i data, controlled through qi order register. for the dual tx data cases, the tx_sync pin input logic level defines what data is currently on the tx data bus. by default, when tx_sync is low, channel a data (first of the set) should be on the data bus. if txsync is high, channel b data (or the second of the set) should be on the tx bus. this can be reversed by setting the inv txsync register. additional features in addition to the features mentioned above in the transmit, receive and clock paths, the ad9860/ad9862 also integrates components typically required in communication systems. these components include auxiliary analog-to-digital converters (aux adc), auxiliary digital-to-analog converters (aux dac), and a sigma-delta output. auxiliary adc two auxiliary 10-bit sar adcs are available for various external signals throughout the system, such as a receive signal strength indicator (rssi) function or temperature indicator. the auxil- iary adcs can convert at rates up to 1.25 msps and have a bandwidth of around 200 khz. the two auxiliary adcs (aux adc a and aux adc b) have multiplexed inputs, so that up to four system signals can be monitored. 00: b = a 01: b = 2 a 10: b = 4 a 00: c = b 01: c = b/2 10: c = b/4 00: d = c 01: d = 2 c 10: d = 4 c adc sample rate (not to exceed 64mhz) dll output rate (not to exceed 128mhz) clkout2 input tx data rate (single channel) txdac update rate single channel (cannot exceed dll output rate) clkin ab cd dll mult clkout2 div interp figure 14. single tx timing block diagram, alternative operation 00: b = a 01: b = 2 a 10: b = 4 a 00: c = b 01: c = b/2 10: c = b/4 00: f = g 01: f = 2 g 10: f = 4 g clkout2 input tx data rate txdac update rate each channel (cannot exceed dll output rate) clkin ab ef dll mult clkout2 div interp 0: d = c 1: d = 2 c c 2 edges e = d/2 d dual channel fac t or adc sample rate (not to exceed 64mhz) dll output rate (not to exceed 128mhz) input tx data rate each channel figure 15. dual tx timing block diagram, alternative operation the aux adc a multiplexer controls whether pin aux_adc_a1 or pin aux_adc_a2 is connected to the input of auxiliary adc a. the multiplexer is programmed through register d34 b1, selecta. by default, the register is low, which connects the aux_adc_a2 pin to the input. similarly, aux adc b has a multiplexed input controlled by register d34 b4, selectb. the default setting for selectb is low, which connects the aux_adc_b2 input pin to aux adc b. if the selecta or selectb register bit is set high, then the aux_adc_a1 pin or the aux_adc_b1 pin is connected to the respective aux adc input. an internal reference buffer provides a full-scale reference for both of the auxiliary adcs that is equal to the supply voltage for the auxiliary adcs. an external full-scale reference can be applied to either or both of the aux adcs by setting the appropriate bit(s), refselb for the aux adc b and refsel a for the aux adc b in the register map. setting either or both of these bits high will disconnect the internal reference buffer and enable the externally applied reference from the aux_ref pin to the respective channel(s). timing for the auxiliary adcs is generated from a divided down rx adc clock. the divide down ratio is controlled by register d35 b0, clk/4 and is used to maintain a maximum clock rate of 20 mhz. by default, clk/4 is set low dividing the rx adc clock by 2; this is acceptable when running the rx adc at rate of 40 mhz or less. at rx adc rate greater than 40 mhz, the clk/4 register bit should be set high and will divide the rx adc clock by 4 to derive the auxiliary adc clock. the conversion time, including setup, takes 16 clock cycles (16 rx adc clock cycles); when clk/4 is set low, divide by 2 mode, or 32 clock cycles when clk /4 is set high.
rev. 0 ad9860/ad9862 ?31? conversion is initiated by writing a logic high to one or both of the start register bits, register d34 b0 (starta) and d34 b3 (startb). when the conversion is complete, the straight binary, 10-bit output data of the aux adc is written to one of four reserved locations in the register map depending on which auxil- iary adc and which multiplexed input is selected. because the auxiliary adcs output 10 bits, two register addresses are needed for each data location. initiating a conversion or retrieving data can also be accomplished either through the standard serial port interface by reading and writing to the appropriate registers or through a dedicated aux iliary serial port interface (aux spi). the aux spi can be configured to allow fast access and control of either one of the auxiliary adcs and is available so that the spi is not tied up retrieving auxiliary adc data. the aux spi can be enabled and configured by setting register aux adc ctrl. setting register use pins high enables the aux spi port. setting register sel bnota low connects auxiliary adc a to the aux spi port, while setting it high connects auxiliary adc b to the aux spi port. as mentioned above, setting the appropriate select bit selects which of the multiplexed input is connected to the auxiliary adc. the aux spi consists of a chip select pin (aux_spi_csb), a clock pin (aux_spi_clk), and a data output pin (aux_spi_do). a conversion is initiated by pulsing the aux_spi_csb pin low. when the conversion is complete, the data pin, aux_spi_do, previously a logic low, will go high. at this point, the user supplies an external clock, previously tied low, no data is present on the first rising edge. the data output bit is updated on the falling edge of the clock pulse and is settled and can be latched on the next clock rising edge. the data arrives serially, msb first. the aux spi runs up to a rate of 16 mhz. aux dac the ad9860/ad9862 has three 8-bit voltage output auxiliary dacs, aux dacs. the aux dacs are available for supplying various control voltages throughout the system such as a vcxo voltage control or external vga gain control and can typically sink or source up to 1 ma. an internal voltage reference buffer provides a full-scale voltage reference for both of the aux dacs equal to the supply voltage for the aux dacs. the straight binary input codes are written to the appropriate registers. if the slave mode register bit is high, slave mode enabled, the aux dac(s) update will occur when the appropriate update register is written to. otherwise, the update will occur at the conclusion of the data being written to the register. typical maximum settling time for the auxiliary dac is around 6 m s. other optional controls include an invert register control and a power down option. the invert register control, i.e., instead of hexff being high and hex00 being low, hex00 is high, and hexff will be minimum setting. sigma-delta a 12-bit sigma-delta (sd) output is available to provide an additional control voltage. the sd control word is written to registers d42, 43; sd [11:4] are the 8 msbs and sd [3:0] are the 4 lsbs. the 12-bit word is processed by a sigma-delta modulator and produces 1-bit data at an oversampled rate equal to 1/8 of the receive adc
rev. 0 c02970?0?11/02(0) printed in u.s.a. ?32? ad9860/ad9862 outline dimensions 128-lead plastic quad flatpack [lqfp] (st-128b) dimensions shown in millimeters compliant to jedec standards ms-026bhb top view (pins down) 1 38 39 65 64 102 103 128 seating plane 1.60 max view a 7 0 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 10 6 2 0.75 0.60 0.45 0.27 0.22 0.17 16.00 bsc 20.00 bsc 22.00 bsc 0.50 bsc 14.00 bsc

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